Hello,
we got this assignment at school about cpu cache. We have a simulator of cpu cache. I can set access time for cache to 10ns and access time for ram to 100ns. So why is the access time from ram 800ns if there is a cache miss? No matter what else i change, there is always such a big delay. This delay is far higher than if the cpu would read direct from ram. If there is a high hit rate, the average access time falls to around 50-60 ns.
we got this assignment at school about cpu cache. We have a simulator of cpu cache. I can set access time for cache to 10ns and access time for ram to 100ns. So why is the access time from ram 800ns if there is a cache miss? No matter what else i change, there is always such a big delay. This delay is far higher than if the cpu would read direct from ram. If there is a high hit rate, the average access time falls to around 50-60 ns.