pelvis_3
HWF Member For Life
San Jose (CA) - P.A. Semi is a new player in the processor market that competes for a portion of the cut-throat CPU market. The company hopes to carve out its place by avoiding direct confrontation with Intel: P.A. Semi's 65 nm low-power dual-core system-on-a-chip design is based on IBM's Power Architecture. Announced today, the first 2 GHz chips are scheduled to sample by Q3 2006.
Low-power processors? Listening to P. A. Semi, we cannot help thinking about another company that was about to take the processor market by storm by introducing a technology that consumed much less power than any other existing chip architecture. Almost six years ago, it was Transmeta that had developed a revolutionary processor that was promised a rosy future - until the first processors were physically available and until Intel had re-directed its marketing forces and product development.
P. A. Semi's approach of a low-power processor sounds very much like Transmeta's strategy at first, but in fact is different in a few key-aspects. The firm's processors, named "PWRficient", are a complete SoC (system-on-a-chip) solution and apparently put a greater focus on performance than Transmeta ever did. "Nobody can touch the processor's performance at a particular power level," said Pete Bannon, Vice President, Architecture at P.A. Semi, in a conversation with TG Daily.
PA Semi
P. A. Semi PA6T-1682M processor
Most important, perhaps, PWRficient is not x86-based and therefore avoids direct competition with Intel and AMD. Instead, P. A. Semi licensed IBM's Power Architecture and sees actually IBM, ARM and Freescale as its initial competitors. But Bannon mentioned that the chip could compete with Intel in higher-end cluster applications one day.
So, what does P. A. Semi offer? The PWRficient is said to debut as 65 nm PA6T-1682M model 200 million transistors. The chip design integrates two 2 GHz cores, each with 64 KByte I-cache and 64 KByte D-cache. The cores are connected through an interface named "Connexium" that connects to 2 MByte shared L2 cache. The bandwidth of the interface is 16 GByte in read and write processes. Other components of the SoC include transaction trace memory, peripheral trace memory, as well as the "Envoi" component as I/O protocol engine that covers PCI Express, dual 10 Gbit Ethernet, I/O cache, DMA and offload engines, for example.
For the future, P. A. Semi says, the design is scalable to eight cores, to 2.5 GHz clock speed and up to 8 MByte L2 cache.
Article - TG Daily
Low-power processors? Listening to P. A. Semi, we cannot help thinking about another company that was about to take the processor market by storm by introducing a technology that consumed much less power than any other existing chip architecture. Almost six years ago, it was Transmeta that had developed a revolutionary processor that was promised a rosy future - until the first processors were physically available and until Intel had re-directed its marketing forces and product development.
P. A. Semi's approach of a low-power processor sounds very much like Transmeta's strategy at first, but in fact is different in a few key-aspects. The firm's processors, named "PWRficient", are a complete SoC (system-on-a-chip) solution and apparently put a greater focus on performance than Transmeta ever did. "Nobody can touch the processor's performance at a particular power level," said Pete Bannon, Vice President, Architecture at P.A. Semi, in a conversation with TG Daily.
PA Semi
P. A. Semi PA6T-1682M processor
Most important, perhaps, PWRficient is not x86-based and therefore avoids direct competition with Intel and AMD. Instead, P. A. Semi licensed IBM's Power Architecture and sees actually IBM, ARM and Freescale as its initial competitors. But Bannon mentioned that the chip could compete with Intel in higher-end cluster applications one day.
So, what does P. A. Semi offer? The PWRficient is said to debut as 65 nm PA6T-1682M model 200 million transistors. The chip design integrates two 2 GHz cores, each with 64 KByte I-cache and 64 KByte D-cache. The cores are connected through an interface named "Connexium" that connects to 2 MByte shared L2 cache. The bandwidth of the interface is 16 GByte in read and write processes. Other components of the SoC include transaction trace memory, peripheral trace memory, as well as the "Envoi" component as I/O protocol engine that covers PCI Express, dual 10 Gbit Ethernet, I/O cache, DMA and offload engines, for example.
For the future, P. A. Semi says, the design is scalable to eight cores, to 2.5 GHz clock speed and up to 8 MByte L2 cache.
Article - TG Daily
